1. Field
Aspects of the embodiment relate to a semiconductor integrated circuit, a memory system, a memory controller and a memory control method.
2. Description of the Related Art
The chip of a synchronous dynamic random access memory (SDRAM) or a flash memory is coupled to the chip of a system LSI including a processor, and the external memory chip is employed as a main memory. In the above-described chip, the mainstream is formed by a configuration wherein the SDRAM of double data rate (DDR) or DDR2 which outputs data at both trailing/leading clock edges is employed in order to heighten the speed of the operation of the system.
When the processor runs a program, it has used a conventional configuration where the memory area of the external chip as described above is not used as a program running area, instead a memory within the system LSI chip, such as a cache or a chip-on memory, is used as the running area. The memory within the system LSI chip is configured of, for example, a static random access memory (SRAM), which can be accessed at high speed.
In recent years, however, with enlargement in the size of the program to-be-run or the capacity of data to-be-processed, the capacity of the memory within the system LSI chip has often become insufficient as the area for running the program. In this case, the memory area of the external memory chip as stated above is directly used as the program running area.
Also in recent years, a plurality of processors have sometimes been installed on a single chip as a system-on chip. In such a case, the memory coupled outside the system LSI is shared by the plurality of processors on account of a limitation in the number of terminals of the LSI and for the purpose of decreasing the packaging area and the number of components.
When the memory is shared by the plurality of masters (the plurality of processors), an access conflict occurs among the masters. When the SDRAM or the flash memory which is used as the external memory, a latency for one access is large. When, for example, the SDRAM, a time period of 4 to 5 clock cycles is required from “bank-active” until first data is output. Accordingly, data should be read and written using a burst access to the utmost, not a single access. However, a burst operation causes a long time to be expended between the start of access and the end of data input/output in order to successively input/output data, and the other master which is not accessing the external memory needs to wait for its access. Thus, access latency increases, and the processing performance of the processor lowers.
The conventional memory system has the problem that the increase of the latency at the occurrence of the conflict of access to the external memory cannot be suppressed when the external memory is shared by the plurality of masters.